A Capacitive In-Memory Computing Unit for Vector-Matrix Multiplication

This paper presents a novel in-memory computing unit (IMCU) architecture that utilizes a fully analog capacitor-based design to perform vector-matrix multiplications using only the energy from the input. The architecture requires no additional circuitry apart from switches to carry out multiply and accumulate operations. To achieve the resolution of the synaptic weights, a configurable capacitor circuit has been used. We evaluate the speed limitations, as well as attainable input and weight resolutions for this architecture using a 130 nm CMOS technology. The designed in-memory computing unit demonstrates 6-bit input and 6-bit weight resolution, while consuming an average of only 80.9 fJ of energy per multiplication element. The proposed IMCU architecture is fully compatible with any kind of standard commercial CMOS process.