A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application

For increasing consumers’ needs for processing data at high speed and low power consumption in mobile devices and automotive applications, LPDDR DRAMs have been much more challenged and struggled for achieving high data bandwidth without increasing power consumption. To meet these trends, many papers like [1], [2] have introduced new I/O circuitry techniques for LPDDR DRAMs because I/O circuitry is one of major points for achieving not only low power consumption but also high data bandwidth. This paper proposes new I/O schemes: a sense-amplifier with AC-coupled equalizer (ACCE), a stacked output driver, and a duty-immune clock multiplexer (CLKMUX). The ACCE enhances a write (WR) I/O margin while minimizing an increase of input capacitance during the WR operation. And the stacked output driver improves a read (RD) I/O margin reducing a power consumption during the RD operation. Finally, the CLKMUK also increases a RD I/O margin by removing an effect of duty variations on internal clock. By adopting the proposed I/O schemes, the measured WR I/O margin is improved by 28% and the RD I/O margin also improved by 20% with reducing the power consumption of 21% compared to the previous LPDDR4/4x DRAM products.