A Digitally Calibrated 1 ^st Order Noise Shaped SAR ADC in 28 nm CMOS

This paper proposes techniques to achieve lower thermal noise in the loop filters of NS SAR ADCs. An error feedback topology is used to build a more robust filter without integrators. A first order topology is chosen to reduce thermal noise and novel cascade of dynamic amplifiers are used to avoid the series switches on top-plate capacitor node of SAR ADC. On-chip digital calibration is used to enhance the performance of an ADC. A protoype of Noise Shape SAR ADC is fabricated in 28 nm CMOS technology to demonstrate these techniques. Measurements shows that the proposed architecture achieves SNDR and SFDR of 78.5 dB and 82.9 dB respectively.