A Charge Injection Neutralization Technique for Wide-Band Interleaved DAC

This paper presents a novel current-steering RF DAC design in 28nm CMOS FDSOI technology. The architecture enhances linearity, minimizes energy consumption, and ensures scalability for high-frequency applications. It includes a modified differential pair with neutralizing capacitors, cascode transistors, and body-biasing to mitigate charge injection and Miller effects. The low-power design enables high interleaving capacity, suitable for interleaved Digital-to-Analog Converters (DAC). Simulation results show an 8GHz maximum frequency and 2.504mW power consumption, making it a promising candidate for efficient high-performance RF applications.