Transistor Sizing Optimization for Improved Radiation Hardening in 2: 1 MUX Designs

The evolution of circuit manufacturing technology has allowed for greater integration of these components. To achieve this, the dimensions of the transistors have been reduced, as well as their supply voltage, significantly impacting the reliability of these circuits. In this context, transient faults are recognized as a major threat to electronic devices. Multiplexers are used in digital circuits, acting as a data selector switch, therefore, a fundamental circuit for numerous logic applications. The objective of this work is to analyze the robustness of six different 2: 1 multiplexer designs, considering the area of the largest circuit. For this, the sensitive regions were analyzed, and a transistor sizing technique was applied according to the susceptibility of each circuit. The circuit analysis was performed by identifying the sensitive nodes in the transistor arrangement, and based on this information, electrical simulations were carried out to determine the minimum critical charge value required to cause a fault. With these values, the critical charge was calculated. The new sizing explored showed gains of up to 2x in the multiplexer robustness. This result demonstrates the importance of exploring radiation hardening techniques.