A 5.7-7.2 GHz Receiver Front-End with Improved Harmonic Selection Using a 6-Phase Non-Overlapped Clocking System

An RF wideband harmonic selection receiver front-end using multi-phase non-overlapping LO clocks based on a delay locked loop (DLL) is presented to provide programmable notches at any undesired LO harmonics. The proposed receiver front-end uses a non-overlapped clocking scheme that tunes the duty cycle to select the third harmonic of the switching frequency while suppressing the other LO harmonics, especially the first. Third harmonic selection rather than the fundamental reduces the required input frequency of the multi-phase clock generator at higher frequencies. The 5.7 -7.2 GHz clock-based receiver front-end is implemented in a 65 nm CMOS process and provides a post-layout simulated harmonic rejection ratio of 77 dB for the first LO harmonic. The front-end exhibits a noise figure of 4.9dB at a baseband frequency of 90 MHz for a 5.7GHz RF input signal.