ASCEND: Advanced Synthesis, Circuit Exploration, and Design Optimization for NCL Circuits

Null Convention Logic (NCL) is a popular asynchronous design paradigm that, in contrast to its synchronous counterpart, demonstrates robustness, ultra-low power performance, and ease of design reuse, while avoiding the complex clock management issues. Despite these advantages, the lack of mature computer-aided design tools has limited the widespread adoption of the domain across the industry. To address this gap, we present herein a novel framework, ASCEND, to facilitate the automated synthesis of NCL circuits with enhanced optimization capabilities. ASCEND includes multiple NCL protocol and equivalence verification schemes, as well as supports the synthesis of a pareto-optimal design in terms of throughput or area, contingent upon the target requirement. The performance and efficacy of the framework have been validated using multiple IWLS and ISCAS benchmark circuits.