Three-Level Space Vector Modulation Method for Common-Mode Voltage Suppression

Three-level Neutral-Point-Clamped (NPC) topology are extensively utilized in motor drive applications. However, two prevalent issues associated with Three-level NPC inverters are neutral-point (NP) fluctuations and common-mode voltage (CMV) suppression. To address these problems, an improved modulation strategy is proposed that effectively mitigates NP voltage imbalance and CMV. This strategy achieves CMV suppression by selecting vectors that produce smaller CMV for vector synthesis. For the NP voltage balance, it employs the selection of either a P/N type vectors while adjusting the action time of these vectors. Compared to traditional space vector pulse-width modulation (SVPWM) strategies, this approach simultaneously reduces NP voltage deviation and CMV. Furthermore, the expression for neutral-point current under this modulation strategy is derived, providing a practical method for the design of DC-side capacitors in three-level NPC inverters.