Optimizing Computational Efficiency: In-Memory Computing with Dynamic Switching

Modern computing architectures mainly utilize the Von-Neumann architecture. However, the increasing demand for processing vast volumes of data worsens the Von-Neumann bottleneck, which results in significant energy consumption and computational latency. In-memory computing provides an effective solution for Von-Neumann bottleneck by performing fundamental logical or arithmetic operations inside the memory directly. In this paper, an in-memory computing architecture with dynamic switching function is proposed to provide multiple logical or arithmetic operations. The 8+T SRAM cell and pass transistor logic circuits are utilized in the proposed in-memory computing architecture. Specifically, we introduce the design of a dynamic adder-subtractor capable of switching between addition and subtraction, thereby enhancing the efficiency of in-memory computing.