Accelerated Real-Time Local Maxima Detection in Video Streams Using FPGA Technology

In this paper, we present a successful implementation of a local maxima filter on a Zybo Z7-20 and PYNQ Z1 FPGA using their two HDMI ports in real-time. The proposed system uses the HDMI ports to capture video frames with a resolution of 640x480 pixels. The local maxima filter is then applied to the captured frames in real-time, allowing for the detection of peaks in the image data. The filter uses a sliding window approach to determine the local maxima, and a threshold value is set to identify and retain only the most significant peaks in the image. The system was implemented using SystemVerilog Hardware Description Language (HDL). The system was developed in the Xilinx Vivado design suite and the results show that the proposed system is able to process video frames at a rate of 60 frames per second with high accuracy and low latency. The proposed implementation using SystemVerilog presents a more efficient and flexible solution for image processing applications on FPGA, making it a promising approach for real-time image processing.

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Publication Details

Published
2024-12-03
DOI
https://doi.org/10.1109/apsipaasc63619.2025.10848897
Primary Topic
Image and Signal Denoising Methods
Type
article
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article

Accelerated Real-Time Local Maxima Detection in Video Streams Using FPGA Technology

Yahwista Salomo, Rahmat Mulyawan, Trio Adiono, Infall Syafalni et al.
Image and Signal Denoising Methods
article

Accelerated Real-Time Local Maxima Detection in Video Streams Using FPGA Technology

Yahwista Salomo, Rahmat Mulyawan, Trio Adiono, Infall Syafalni, Nana Sutisna, Anindhita Nayazirly Sukarno
article en

Abstract

In this paper, we present a successful implementation of a local maxima filter on a Zybo Z7-20 and PYNQ Z1 FPGA using their two HDMI ports in real-time. The proposed system uses the HDMI ports to capture video frames with a resolution of 640x480 pixels. The local maxima filter is then applied to the captured frames in real-time, allowing for the detection of peaks in the image data. The filter uses a sliding window approach to determine the local maxima, and a threshold value is set to identify and retain only the most significant peaks in the image. The system was implemented using SystemVerilog Hardware Description Language (HDL). The system was developed in the Xilinx Vivado design suite and the results show that the proposed system is able to process video frames at a rate of 60 frames per second with high accuracy and low latency. The proposed implementation using SystemVerilog presents a more efficient and flexible solution for image processing applications on FPGA, making it a promising approach for real-time image processing.

Bandung Institute of Technology (ID)
Affordable and clean energy
Openalex Percentile: Top 74%
Image and Signal Denoising Methods
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