Optimized Multi-Processor System-on-Chip (MPSoC) Design for Low-Resource JPEG Encoding

This paper presents the design and optimization of a Multiprocessor System-on-Chip (MPSoC) architecture for low-resource JPEG encoding. The initial design employs six Central Processing Units (CPUs) to implement a pipelined JPEG encoder, divided into stages: color space conversion, level shifting, discrete cosine transform (DCT), quantization, Huffman encoding, and output buffering. The pipeline is then optimized using custom hardware components, including First-In-First-Out (FIFO) queues, custom instruction blocks, and superscalar pipelines to improve performance and efficiency. The paper details the design process, various optimization strategies, implementation challenges, and the resulting performance improvements. The system is implemented and evaluated using the Cyclone IV E Field Programmable Gate Array (FPGA) platform with Nios II/e processors, and the design was developed using the Quartus II software, demonstrating significant gains in throughput and resource efficiency.