Architecture for Error Detection and Recovery in MPSoCs: A Hypervisor Approach Using Dynamic Partial Reconfiguration

This work presents a multiprocessor system-on-chip (MPSoC) architecture for high-reliability space applications that uses a hardware Hypervisor for the programmable logic (PL) to correct single-event upset (SEU) effects by dynamic partial reconfiguration (DPR). The Hypervisor can manage the use of redundant blocks by detecting errors in the blocks and isolating and recovering the wrong blocks transparently. Moreover, the Hypervisor offers an improved error detection latency. Compared to the same architecture without the Hypervisor, it speeds up error detection by more than two orders of magnitude. With the aid of the Hypervisor, the architecture is capable of offering highly localized error detection. The proposed architecture has been validated with both fault injection and irradiation campaigns. Experimental results with proton and neutron irradiation show the capabilities and effectiveness of the presented approach in an MPSoC platform. An improvement of 23% in timeout errors and 26.19% in data errors are obtained compared to the same architecture without the proposed Hypervisor. Furthermore, DPR reduces the time needed to recover from a persistent error in the configuration memory and improves system availability time compared to systems using full reconfiguration mechanisms and scrubbing.