Scalable Vertical In–Ga–As Nanowire MOSFET With 67 mV/dec at 126μm Gate Width

Heterogeneous integration of III-V narrow bandgap transistors on silicon technology is desirable for high frequency circuit implementations. Such high-speed transistors must, however, scale to large gate widths to be suitable for general circuit design. Averaging among many variable channels is a key challenge for nanowire devices. A simplified, but high-speed compatible, nanowire device process was developed here. It utilizes metal plugs to reduce complexity in the gate patterning step. It also implements a spin coated BCB low-k dielectric as top interlayer. A vertical In-Ga–As MOSFET with 1600 nanowire channels and 110 nm gate length achieved a minimum subthreshold swing of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {67~\mathrm{mV/dec} }$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {126~\mu \text {m} }$ </tex-math></inline-formula> gate width. The maximum transconductance was <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {0.88~\text {m}\text {S} /\mu \text {m}}$ </tex-math></inline-formula> at 0.5 V drain-source voltage, with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {0.22~\text {m}\text {A} /\mu \text {m}}$ </tex-math></inline-formula> normalized drain current. These long-channel results are on par with state-of-the art, but achieved for a device scaled to unprecedented device width. In tandem with the BCB interlayer, these results promise a back-end-of-line compatible high-speed vertical nanowire technology for integration on silicon.