State-of-the-Art ASCON ASIC Achieving 4.3 [email protected] and 3.5Tb/[email protected] Outperforming AES by 25 Times

NIST selected ASCON as the standard Lightweight Cryptography (LWC) algorithm in 2023. ASCON’s implementations promise bringing lightweight Authenticated Encryption (AEAD) to resource-constrained devices surpassing Advanced Encryption Standard (AES) implementations. In this work, a standard compliant ASCON Application Specific Integrated Circuit (ASIC) hardware (HW) is designed and fabricated using CMOS GF22FDx technology. This study provides a quantitative assessment of the HW with two other standard compliant implementations of ASCON. One is software implementation (SW), and the other is a hardware accelerated (HW/SW co-design) implementation. The assessment shows that HW outperforms the SW implementation by up to three orders of magnitude in energy efficiency and throughput, whereas HW/SW co-design throughput and energy efficiency falls in the middle between HW and software. ASCON ASIC HW is also compared with a standard HW implementation of the AES fabricated over the same chip. ASCON uses only 39% of AES’s area and boosts energy efficiency by up to 25 times. To the best of our knowledge, this work is the first work providing a silicon-based analysis for ASCON ASIC implementation reaching a throughput of 4.3 Gbps @ 0.8V and 2 Gbps @ 0.6V, and energy efficiency of 1.9 Tb/J @ 0.8V and 3.5 Tb/J @ 0.6V in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2505~\mu $ </tex-math></inline-formula> m2 on GF22FDx at 620MHz @ 0.8V. Furthermore, the comparative assessments between different implementations of ASCON guides the implementation choice for specific deployments to meet the demands of secure processing in dust-size sensors, edge and IoT.