Effects of Bottom Channel Coverage Ratio on Leakage Current and Static Power Consumption of Vertically Stacked GAA Si NS FETs

The performance of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) field-effect transistors (FETs) is significantly impacted by the non-ideal characteristics of the bottom channel, primarily due to etching process limitations. These issues lead to variations in the coverage ratio of the bottom channel, which impacts key device characteristics like leakage current and static power consumption. In this study, we used experimentally calibrated 3D device simulations to analyze the effects of varying bottom channel coverage ratios from 60% to 100% on the GAA Si NS n-/p-type FETs for sub-2-nm technology nodes. Our results reveal an inverse relationship between the coverage ratio and leakage current and static power consumption. Notably, n-/p-type devices at 60% bottom channel coverage ratio exhibiting leakage currents 75.6 and 102.7 times higher than those with 100% bottom channel coverage ratio. This increase is linked to substantial variations in the off-state conduction (18.5%, 75 meV for n-type FETs) and valance (15.3%, 57 meV for p-type FETs) band energies. An 80% bottom channel coverage ratio proves to be an effective compromise, reducing parasitic leakage while addressing manufacturing feasibility. However, achieving a 100% bottom channel coverage ratio remains a critical challenge, highlighting the need for further research on fabrication optimization.