Research on Weight Update Modulation of Memflash for Adaptive Circuits

Different from traditional binary iterative weight update methods, neuromorphic chip, in favor of analog computation based on physical laws, has significantly enhanced computational efficiency. As a typical component of neuromorphic chip, memristor faces the limitation of resistance fluctuation, stability and adjustment range in weight updating control. To overcome these defects, this study proposes an innovative design of a common-gate non-conjugated memflash. Utilizing advanced transfer layer stacking technology, the dynamic range of weight updates has been significantly expanded from 1.87×10⁻⁹A to 4.41×10⁻⁷A, providing a broader adjustment space for neuromorphic computing. Additionally, through customized molecular interface modification technology, the accuracy of weight updates has been improved and a weight update relaxation model has been established, achieving precise and controllable weight adjustment. At the device array level, by adopting a strategy of common-source and common-gate grounding with independent drain control, the crosstalk between devices has been effectively eliminated. This provides a stable foundation for the array to perform matrix-vector multiplication (MVM) operations. The common-gate non-conjugated memflash proposed in this study has not only optimized the weight update mechanism but also enhanced the computational control capabilities of hardware adaptive circuits.