A 13-b 20-MS/s SAR ADC with Capacitor mismatch Calibration combining ADC Self-Calibration

This paper presents a 13-b, 20-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC). A capacitance mismatch calibration method based on the time domain comparator and time-to-digital convert (TDC) combining SAR ADC self-calibration is proposed to achieve high precision. The calibration circuit looks simple enough, and the calibration process costs just 23us. A capacitor with a capacity of only 1fF is designed to be used as a unit capacitor to improve the speed and accuracy of voltage setting. The simulation result shows that the signal-to-noise distortion ratio (SNDR) of ADC is up to 80.62dB, and the spurious-free dynamic range (SFDR) is 95.9dB at a supply voltage of 1.2V and a sampling rate of 20 MS/s.