THERMAL-AWARE TEST SCHEDULING AND FLOOR PLANNING FOR THREE-DIMENSIONAL STACKED INTEGRATED CIRCUITS

Testing three-dimensional stacked integrated circuits (3D-SICs) remains a challenging task due to the complexity of generating an optimized test schedule that minimizes test time. One of the main challenges is accessing upper dies, which is only possible through the bottom die, requiring the extension of Test Access Mechanisms (TAMs) via Through-Silicon Vias (TSVs). Additionally, the limited number of primary I/O pins, TSVs, and TAM width necessitates efficient resource allocation. Effective thermal management is crucial due to the high-power consumption of cores and uneven power distribution, which pose overheating risks. Advanced concurrent test scheduling is essential to allocate resources effectively while maintaining power and temperature limits. This research proposes a thermal-aware test scheduling optimization combined with floor planning for 3D-SICs, where the floor planning is computed using a simulated annealing algorithm based on a set of pareto optimal cubes chosen by an Ant Colony Optimization (ACO) algorithm. The subsequent thermal-aware 3D-SIC test scheduling, considering resource and power constraints, is generated using a 3D Bin Packing method. The objective is to minimize test schedule time while considering resource and power constraints. Experimental results using multiple ITC'02 benchmark circuits indicate an average estimated improvement of 0.25% in test schedule efficiency when incorporating floor planning into test scheduling, compared to scheduling without floor planning. These findings underscore the significance of integrating thermal-aware test scheduling with floor planning, highlighting its potential to significantly enhance test efficiency, reduce power consumption, and ensure reliable testing of 3D-SICs under stringent resource and thermal constraints.