Performance Augmentation, Parameter Modeling and Analysis of Nano-DG-TFET

- In this manuscript, we propose and analyze the properties of an efficient Nano strained-silicon dualhalo high-K dielectric stacked multi-material dual-gate TFET device (Nano-DG-TFET). Compact precise models for this projected Nano TFET are mathematically proposed for the electric field, surface potential, drain current and threshold voltage. Using gate and channel (G&C) engineering, the models are derived by solving the 2-D Poisson equation in silicon-graded channel region by applying suitable boundary conditions. The realtime values of the devices diverge due to various SCEs, second-order effects, and non-idealities present in the device. Hence, the proposed models incorporate the effects of various device parameters such as channel potential, electric field, DIBL, threshold voltage roll-off, and drain current. Also, the fringing capacitance characteristics of the proposed Nano-DG-TFET demonstrate superior performance over Triple Material Double Gate (TMDG) and Single Material Double Gate (SMDG) TFET structures. The proposed Nano-DG-TFET incorporates many other efficient device properties like strained silicon (s-Si) channel, halo implantation, highK dielectric gate stack, triple material gate terminal, and many more. Therefore, it is evident that the proposed nanodevice structure provides poor outflow current IOFF (10−16A/μm), and remarkable betterment in ON current ION (10−6A/μm). The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes to validate the robustness of the model.