Routing in 2.5D FPGAs: How long should interposer lines be?
Interposer-based multi-die FPGAs (2.5D) are composed of multiple dies interconnected externally via wires, allowing the creation of FPGA systems with increased capacity. These external connections are generally fewer than the die's internal interconnection network and contribute to a higher delay and wirelength. These architectural limitations must be considered while optimizing PnR tools for multi-die solutions. The configuration of the interposer interface plays a crucial role in determining the routing resource availability at the die boundary and in ensuring congestion-free solutions. Interposer wires are generally designed to be thicker than the wires in the die's internal interconnection network, and their length can significantly impact overall delay. Longer interposer wires allow longer strides across the die, reducing the need for additional internal routing resources to handle cross-die net routing. Given these conflicting factors, it is crucial to determine an optimal length for the interposer wires. In this study, we aim to investigate how the length of the interposer wire influences the overall performance of PnR tools. We have developed a multi-die placer, LiquidMD and router, CRouteMD capable of accommodating various interposer lengths and have analyzed the impact of interposer length on the quality of PnR. Using a flexible interposer interface based on Xilinx's Virtex-7 architecture, we investigated wire lengths ranging from L12 to L48. In our comparison of PnR results across various interposer wire lengths, ranging from L12 to L48, we found that an optimal interposer wire length of approximately 14% of the die height (L30) improves the overall routing performance. This length of interposer wire reduces the CPD by 5% as compared to the longest interposer wire length which covers 22% of the die height.
Authors
- Dirk Stroobandt (ORCID: https://orcid.org/0000-0002-4477-5313)
- Raveena Raikar (ORCID: https://orcid.org/0000-0002-7344-2518)
Institutions
- Ghent University Hospital (BE)
Publication Details
- Published
- 2024-10-31
- DOI
- https://doi.org/10.1145/3708358.3709349
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00