A Hardware Unit for Single-Precision Floating-Point Inverse Square Root with Harmonized Parabolic Synthesis

In this work, we propose a novel method based on Harmonized Parabolic Synthesis, which combines parabolic synthesis and second-degree interpolation, to implement inverse square root hardware for IEEE single-precision floating-point format on FPGA. The implementations meet the precision requirement of 1 ULP.The experimental results show that the proposed implementation demonstrates either lower resource usage, shorter execution latency, higher clock rate, or higher throughput when compared to other works (including Intel IP), which use various methods such as polynomial approximation and enhanced Quake algorithm.The presented floating-point inverse square root unit is suitable for high-performance embedded systems due to its small size, low latency, and high throughput. It can be used as a stand-alone accelerator or integrated into a processor’s ALU or FPU.