A Hardware-friendly Image Mapping Parameter Matrix Compression Algorithm

Image mapping is widely applied in various fields of multi-camera video, panoramic display, medical imaging, and AR augmented reality. Generally speaking, its software implementation is a computing-intensive task and its hardware implementation needs a lot of both hardware computing resources and storage space. In order to attack such disadvantages, an efficient and hardware-friendly image mapping parameter matrix compression algorithm based on bilinear interpolation has been proposed. The proposed algorithm can theoretically achieve compression ratio with any scale and any image size, which largely benefits its circuit acceleration. The proposed algorithm has been evaluated on image quality from both subjective and objective perspectives based on both USIS-D dataset and a self-shot data, meanwhile it has been verified on a Xilinx Kintex7-325T FPGA board. Experimental results demonstrated that the proposed algorithm significantly cuts down computation and storage resource consumption under the premise of losing little image quality.