High speed near threshold schmitt-trigger transmission gate based 11T CNTFET SRAM cell

The exceptional transport characteristics, better current performance, and improved gate control of CNTFET makes them a highly potential substitute for conventional CMOS transistors. In this study a high speed near threshold (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) Schmitt-trigger transmission gate based 11 transistor (STTG 11T) CNTFET SRAM cell is introduced to improvise delays and I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ratio. The proposed STTG 11T demonstrates up to 2.22×/124.45×/1.62×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup>× better read delay (T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RA</inf>), write delay (T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WA</inf>), and I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ratio respectively, in comparison to the other cells that are being examined. It shows a comparable leakage & dynamic power consumption, as well as read and write stability. The simulation runs with a supply voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>) of 0.43 V using the Stanford University 32 nm CNTFET model and Cadence Virtuoso.