A 14-bit Pipelined-SAR ADC With Offset and Bit-Weight Calibration Techniques

This work presents a 14-bit 100 MS/s Pipelined Successive-Approximation-Register (SAR) ADC in a 28nm CMOS process. The proposed calibration technique remedies the offset voltage and bit-weight deviations that include capacitor mismatches and inter-stage gain error. The comparator offset calibration scheme employs a shift-bit logic together with an R-2R digital-to-analog converter (DAC). An improved SAR logic circuit is also proposed to generate asynchronous timing and store the results. The capacitor mismatches are calibrated in a foreground way while the inter-stage gain error is corrected in a background way using least mean square (LMS) algorithm. With the above calibration and circuit techniques, the spurious-free-dynamic-range (SFDR) is improved to 90.64dBc, while the effective-number-of-bits(ENOB) is 11.89-bit. The 14-bit 100 MS/s ADC is simulated in a 28nm CMOS process and the figure of merit (FOM) value achieves 10.86 fJ/conversion-step.