A 6-9GHz DTC-based Fractional-N Sub-sampling PLL

In this paper, a digital-to-time converter (DTC)-based fractional-N sub-sampling phase locked loop (PLL) based on 28nm CMOS technology is presented. The PLL achieved an output frequency range of 6GHz to 9GHz with a power consumption of 37mW. Specifically, at an output frequency of 7.975GHz, the fractional spur with a 30% DTC gain error is - 58.75dB. After gain calibration and threshold mismatch calibration, the fractional spur is reduced by 11dB to -69.8dB. Furthermore, the phase noise is -116dBc/Hz@1MHz, and the rms jitter is 113fs.