An Embedded Approach towards Power Hardware-In-Loop (PHIL) Simulation of Grid Connected Inverters (GCIs)

This paper deals with the Power-Hardware-In-the-Loop (PHIL) simulation of Grid Connected Inverters (GCIs). The inductive nature of the Device-under-Test (DUT), i.e., GCIs, system impedance, and the delays in the loop create simulation stability challenges. This paper presents an embedded approach towards PHIL testing of GCI DUTs. In this approach the DUT model is represented in real-time simulation process based on a technique similar to that of representing component models in an Electromagnetic Transient (EMT) program. This means the model, representing the DUT, includes admittance and history source elements. To account for the delay in the loop, a Quasi Multi-Rate (QMR) integration method is employed to discretize the DUT model and obtain the admittance element. The history source values are obtained based on the DUT state variable measurements. The approach is applied to a GCI and the results are presented which demonstrate practical delay compensation, i.e., improved stability characteristics while maintaining accuracy. To examine the stability and accuracy of the PHIL test, before closing the loop, a step-by-step procedure based on frequency scanning is presented.