A 60-GHz Distributed CTLE with Complementary Units for 240-Gb/s Receiver in 28-nm CMOS

This paper presents a distributed CTLE with complementary unit as the analog front end of 240-Gb/s wireline receivers. By distributing more CTLE units among the artificial transmission lines, the DC gain of the CTLE can be increased without reducing bandwidth or degrading impedance matching. Compared to lumped CTLEs which realize a high peak gain by cascading multiple stages, the single-stage distributed CTLE achieves higher peak frequency and linearity. To enhance power efficiency, the CTLE unit is implemented with a complementary structure and common-mode feedback, which allows zero voltage drop on the termination resistors. Implemented in a 28-nm CMOS process, the proposed CTLE achieves an 11.1 dB peak gain at 60 GHz with only 60 mW power consumption. It can compensate for a 10.1 dB channel loss with an output amplitude larger than the input.

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Publication Details

Published
2024-09-20
DOI
https://doi.org/10.1109/iccs62517.2024.10846602
Citations
1
Primary Topic
Photonic and Optical Devices
Type
article
Field-Weighted Citation Impact
0.21
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article

A 60-GHz Distributed CTLE with Complementary Units for 240-Gb/s Receiver in 28-nm CMOS

Weixin Gai, Bingyi Ye, Boyang Zhang, Fangzhu Li
1 citations
Photonic and Optical Devices
0.21
article

A 60-GHz Distributed CTLE with Complementary Units for 240-Gb/s Receiver in 28-nm CMOS

Weixin Gai, Bingyi Ye, Boyang Zhang, Fangzhu Li
article en
1 citations

Abstract

This paper presents a distributed CTLE with complementary unit as the analog front end of 240-Gb/s wireline receivers. By distributing more CTLE units among the artificial transmission lines, the DC gain of the CTLE can be increased without reducing bandwidth or degrading impedance matching. Compared to lumped CTLEs which realize a high peak gain by cascading multiple stages, the single-stage distributed CTLE achieves higher peak frequency and linearity. To enhance power efficiency, the CTLE unit is implemented with a complementary structure and common-mode feedback, which allows zero voltage drop on the termination resistors. Implemented in a 28-nm CMOS process, the proposed CTLE achieves an 11.1 dB peak gain at 60 GHz with only 60 mW power consumption. It can compensate for a 10.1 dB channel loss with an output amplitude larger than the input.

Peking University (CN)
Affordable and clean energy
Openalex Percentile: Top 44%
Photonic and Optical Devices
0.21
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