Design of a Low-power, High SNR Rolling Shutter 64-stage TDI Image Sensor

The paper proposes a high-speed, high signal-to-noise ratio (SNR) 64-stage time delay integration (TDI) image sensor. To improve the line rate of the sensor, we partition the pixel array along the horizontal direction and read pixel information from both sides towards the middle. Additionally, we introduce a bypass current in the readout circuit to speed up clamp circuit establishment. Moreover, this sensor achieves better SNR performance due to noiseless charge transfer in the charge domain and noise robustness of the open-loop comparator. The proposed technique is experimentally verified on a 512 × 128 pixel TDI image sensor fabricated using a 55 nm CMOS process. Test results demonstrate that at a line rate of 3980 lines/s, the SNR can reach 67 dB at 64 stage. Compared with other work, there is an increase of 2.7% in line rate and 16.7% in SNR while maintaining low power consumption.