Implementation of Memristor-Inspired Amplifier in Digital Logic Circuits

In this paper, we present the design, implementation, and evaluation of digital logic circuits using memristor-based technology. The focus is on basic gates, a 2 × 1 multiplexer (MUX), a full adder, a full subtractor, and an amplifier, all implemented using the Cadence Virtuoso platform. The memristor model employed here shows significant improvements in power efficiency, area reduction, and speed compared to traditional 45-nm CMOS technologies. Our results demonstrate that memristor-based circuits can achieve up to 71.4% reduction in area, 40% reduction in power consumption, and 54% reduction in delay, highlighting the potential of memristor technology for future low-power, high-performance digital systems.