A High-Speed Asynchronous SAR ADC Employing Metastability Detection and Hardware Reused Skip Technique

A single-channel high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Considering that the metastability error occurs when the input signal is approximately equal to zero, a novel metastability error detection technique is presented. Moreover, based on this, a hardware reused skip technique is proposed to relax the timing design requirement in SAR logic loops. These techniques enable a 500 MS/s 9-bit asynchronous SAR ADC in a 22-nm CMOS process. Simulation results show that the proposed techniques help to reduce the metastability error, increase the conversion speed, and improve the power efficiency of the SAR ADC.