A 2-18 GHz, 6-bit True Time Delay Chain with 378 ps Delay

In this paper, we introduce a highly integrated 6-bit 2-18 GHz true time delay (TTD) circuit for multi-band phased array systems covering S-band to Ku-band based on 130 nm SOI technology. 3D electromagnetic simulation is optimized for the artificial transmission line (ATL) and all-pass network (APN) units in the delay chain to achieve a smaller on-chip area footprint. The TTD designed in this paper has a maximum delay of up to 378 ps, a minimum step of 6 ps, a root-mean-square (RMS) error of less than 8.14 ps, and a maximum insertion loss of less than 18 dB. The entire ultra-wideband delay circuit and the related functional modules are described in this paper, which has been verified by post-simulation and is now in the process of tape out.