Performance Optimization After Hardware Security in Analog Integrated Circuits

In recent years, hardware security has become a significant concern in both the design and the production phases for electronic devices worldwide. Violations of a designer's intellectual property pose substantial financial challenges. While various research studies on hardware security have focused on defence strategies, attack methods, and generally securing a design, the effects on the design process are often overlooked. However, many locking mechanisms significantly impact circuit performance, especially in analog circuits. This impact makes the design process longer and more laborious. In this work, we resize transistors in a circuit after locking using automation to obtain the performance before security or better. With this approach, we propose a combination of optimization methods with security implementations to achieve an optimum security integration process.