Impact of Gate Oxide Thickness Variation on the On-state Safe Operating Area and FoM of SOI-Junctionless FinFET considering the Self-heating Effects

A 3D Silicon On Insulator-Junctionless FinFET (SOI-JLFinFET) device structure has been simulated to explore the impact of gate oxide thickness (t<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf>) variation on performance metrics such as breakdown voltage, maximum drain current, and the safe operating area (SOA). To analyze the SOA thoroughly, simulations are done for SOI-JLFinFET with oxide thicknesses ranging from 2 nm to 5 nm. The effect of t<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf> on the peak temperature of SOI-JLFinFET is also studied. The distribution of the electric field vector in the channel region has been examined for both thin and thick gate oxides. The device’s performance for amplification application has also been assessed by obtaining the transconductance (g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf>) at different drain voltages. Furthermore, the overall effect of gate oxide thickness (t<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf>) variation on the on-state breakdown voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br,ON</inf>) and maximum drain current(I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,max</inf>), which impact the device’s power handling capability and Figure of Merit (FoM) have been studied.