Implementation of the YOLOv8 Convolutional Neural Network Block on FPGA

Hardware implementation of Convolutional Neural Networks (CNNs), a key AI topic recently, is as important as the algorithm itself. The computational intensity, reaching millions of operations, has driven efforts to enhance speed, energy efficiency, and resource use. Based on this, we designed and implemented the first layer (16 channels) of the YOLOv8n object tracking algorithm on an FPGA using various hardware architectures. For this purpose, we utilized parallelism, pipelining techniques, and hard-wired block RAMs. We designed ten different CNN IP cores using VHDL. We tested the system containing each IP structure at 100-150 MHz and the IP cores themselves at 200-250 MHz. In these tests, we processed a 640x640x3 image through 16 filters of 3x3x3 size. Our design, taking only 0.141 seconds, operates 648 times faster than an ARM A9 processor embedded in the FPGA, and 2.8 times faster than a PC with an i7-6700HQ CPU and 8GB of RAM.