A V-Band Linear Power Amplifier with 20.4-dBm Psat and 17.5-dBm OP1dB in 65-nm CMOS

This paper presents a V -band two-stage power amplifier (PA) implemented in 65-nm CMOS technology, featuring a symmetrical two-way parallel power combiner. The design utilizes a cascode amplifier in the power cell and a common-source (CS) amplifier in the driver cell, both integrated with neutralizing capacitors. The PA demonstrates a simulated peak small-signal gain of 18.2 dB and a 3-dB bandwidth of 11.5 GHz. It achieves a saturated output power of 20.4 dBm, an output 1-dB compression point (OP1dB) of 17.5 dBm, and a peak power-added efficiency (PAE) of 13.2%, respectively. The compact core area occupies only 0.125 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>,