A Modulo (2ⁿ - (2^k + 1)) Adder for RNS-based Digital Signal Processing Applications

In this work, a new efficient modular adder that deals with modulus $\left(2^{n}-2^{k}-1\right)$ is proposed, where n is a positive integer and k is a positive odd integer within the range $1 \leq k \leq n-3$. The suggested circuit uses the regular Ladner-Fischer parallel-prefix structure as its main skeleton. This new adder has the same area and time delay requirements of a regular modulo ($2^{n}-1$) adder. The proposed structure is compared with other adders of the same computational functionality using the unit-gate theoretical model and the VLSI realization model. Both models have shown that this new structure outperforms other published structures. The comparison using VLSI synthesis tools has shown that the suggested circuit architecture reduces integrated circuit area, time delay, power consumption, area-delay product, and delay-power product by $(15-57) \%, (15-21) \%,(11-40) \%,(38-81) \%$ and $(33-62) \%$, respectively.