A 192–229-GHz 4.4-dBm CMOS Frequency Tripler With Slotline-Based Drain Harmonic Shaping

Frequency triplers in CMOS processes are seldomly explored in the terahertz (THz) band due to the low output power. To address this challenging issue of output power, this article proposes a drain harmonic shaping method for frequency triplers. For theoretical analysis, a modified Enz-Krummenacher–Vittoz (EKV) model suitable for third harmonic analysis is presented for the first time. Using this model, the optimal waveform at drain is derived and the third harmonic generation is analyzed in detail. Compared to conventional triplers, the proposed approach optimizes harmonic utilization at both the drain and source by enhancing the third harmonic through strengthening the second harmonic at the drain and weakening it at the source. Slotline (SLOT) with common-mode (CM) rejection is used to independently control odd- and even-order harmonics, while the SLOT-based output network is designed for both drain harmonic shaping and power combining. For validation, a frequency tripler in 40-nm bulk CMOS technology is fabricated and measured. The proposed tripler achieves a saturate output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P} _{\text {sat}}$ </tex-math></inline-formula>) of 4.4 dBm at 211.5 GHz with a 3-dB bandwidth (BW) from 192 to 229 GHz and a second harmonic rejection ratio (HRR) larger than 26 dBc. Benefiting from the compact passive networks, the tripler also features a core area of 0.09 mm2 only. To the best of our knowledge, around 200 GHz, the proposed tripler achieves the highest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P} _{\text {sat}}$ </tex-math></inline-formula> among CMOS triplers and is comparable to CMOS doublers.