Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder

Ising machines are efficient hardware solvers for combinatorial optimization problems (COPs). In CMOS-based Ising machines, the annealing process is crucial for efficiently navigating complex energy landscapes in mapped COPs such as Max-Cut and low-density parity-check (LDPC) decoding. QuBRIM, a CMOS-based Ising machine, has recently been utilized to solve LDPC decoding problems using multi-body interactions. A constraint-aware annealing schedule is proposed that increases the efficiency of solving the mapped COP. The proposed annealing method uses knowledge of the LDPC decoding problem to guide the annealing process. The annealing schedule is demonstrated through high-level simulations. The proposed methodology demonstrates a normalized energy efficiency (NEE) of 0.68 pJ/bit/iteration, which is a 1.8x improvement over random bit-flip annealing, and an 80% increase in throughput.

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Publication Details

Journal
IEEE Transactions on Circuits & Systems II Express Briefs
Published
2025-01-22
DOI
https://doi.org/10.1109/tcsii.2025.3532665
Citations
2
Primary Topic
Neural Networks and Applications
Type
article
Field-Weighted Citation Impact
4.96

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article

Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder

Zeljko Ignjatovic, Eslam Elmitwalli, Selçuk Köse
2 citations
IEEE Transactions on Circuits & Systems II Express Briefs
Neural Networks and Applications
4.96
article

Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder

Zeljko Ignjatovic, Eslam Elmitwalli, Selçuk Köse
article en
2 citations

Abstract

Ising machines are efficient hardware solvers for combinatorial optimization problems (COPs). In CMOS-based Ising machines, the annealing process is crucial for efficiently navigating complex energy landscapes in mapped COPs such as Max-Cut and low-density parity-check (LDPC) decoding. QuBRIM, a CMOS-based Ising machine, has recently been utilized to solve LDPC decoding problems using multi-body interactions. A constraint-aware annealing schedule is proposed that increases the efficiency of solving the mapped COP. The proposed annealing method uses knowledge of the LDPC decoding problem to guide the annealing process. The annealing schedule is demonstrated through high-level simulations. The proposed methodology demonstrates a normalized energy efficiency (NEE) of 0.68 pJ/bit/iteration, which is a 1.8x improvement over random bit-flip annealing, and an 80% increase in throughput.

IEEE Transactions on Circuits & Systems II Express BriefsVol. 72(3)
University of Rochester (US)
National Science Foundation, Defense Advanced Research Projects Agency
Affordable and clean energy
Openalex Percentile: Top 6%
Neural Networks and Applications
4.96
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Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder — Zeljko Ignjatovic, Eslam Elmitwalli, et al. · IEEE Transactions on Circuits & Systems II Express Briefs (2025) | TGRS Research Map | TGRS