A 500-kS/s Continuous-Time Linear-Exponential Incremental ADC Achieving 90.1-dB DR and 103.1-dB SFDR

This article presents a continuous-time (CT) linear-exponential incremental ADC (IADC) that achieves 15-bit resolution at 250kHz bandwidth with 40 cycles for one conversion. It is based on an energy-efficient CT linear-exponential IADC, which alleviates the requirements of the power-hungry input buffer and loop filter. The proposed IADC employs a coarse 9-bit first-order IADC followed by a fine 8-bit cyclic ADC. The first-order IADC performs the coarse conversion by linearly accumulating input signals, resulting in a small thermal noise penalty. The residual quantization noise is exponentially reduced by the cyclic ADC, significantly shortening the conversion cycle. The cyclic ADC achieves the required accuracy by reconfiguring the loop filter of the coarse IADC and effectively compensating for the excessive loop delay. The prototype CT IADC is fabricated in a 65-nm CMOS process. With a 20MHz clock, it achieves 88.6-dB SNDR, 89.3-dB SNR, 90.1-dB DR, and 103.1-dB SFDR at a conversion rate of 500 kS/s. It consumes only 2.4 mW from a 1.2 V supply. It achieves the Schreier FoM (SNDR) of 168.8dB.