Preparing Students with Industrial Collaboration in Meeting the Challenges in Engineering Design with Consummate VLSI Education

For in-depth Microelectronics education, state-of-the-art laboratory facilities are required to complement theoretical instructions in order to validate the modeled microelectronic design from its conception to the finished chip along with its real time testing.University laboratory facilities are utilized for a broad range of microelectronic designs but fabrications of complex devices are not often achieved due to the budgetary/equipments limitations.The system design in general and VLSI system in particular needs multidisciplinary skills.The VLSI education model addresses this problem adequately.In order to become an integral VLSI designer one needs to inculcate skills in design, simulation, testing and verification.This requires a special commitment of funds, which are beyond budgetary allocations of the schools.The partnership between academia and industry is of vital importance, especially through sponsorship of UMass Lowell's VLSI Design and Fabrication activities.The VLSI program comprises of four distinct and disparate phases namely-Phase 1: Chip design -This basically involves the design of the chip based on specifications provided by the customer, Phase 2: Mask Set -It involves the conversion of design's layout and placement into set of masks e.g.diffusion, contact, and metallization masks etc., Phase 3: Mask Transfer -This involves transferring the mask set onto a wafer substrate such as Si or GaAs etc., Phase 4: Packaged Chip -This incorporates inscribing, dicing, bonding and encapsulating chip in a plastic or ceramic package, depending on customer's requirement.In order to enhance the design capabilities UMass Lowell received a donation of $28m from Cadence and 50% discount from SUN on sparc stations, with a promise to pay $5k to Cadence for license agreement, which is cardinal stone of Phase I since 1998.Phase II has not been achieved yet at UMass Lowell due to budgetary constraints.Phase 3 however, was consummated in its entirety through Distributed Semiconductor Instructional Processing Laboratory (DSIPL), a unique facility established at UMass Lowell in 1986 with a grant of $1m by M 2 C along with the clean room.The test mask for this endeavor was provided by National Institute of Science and Technology (NIST) and students carry out in-situ testing as well as exhaustive testing in all stages of processing including Oxidation, Lithography, Diffusion, Metallization etc. Phase 4: This phase was not also accomplished because of budgetary and space problems at our place so far.