"IMPARTING CONSUMMATE INSTRUCTIONS IN MICROELECTRONICS ENGINEERING AND VLSI TECHNOLOGY AT THE UNIVERSITY OF MASSACHUSETTS, LOWELL"

For consummate VLSI program, theoretical instructions must be complemented with adequate laboratory facilities in order to validate the design from its conception to the finished chip along with its real time testing.This comprises of four distinct and disparate phases namely-Phase 1: Chip design -This basically involves the design of the chip based on specifications provided by the customer, Phase 2: Mask Set -It involves the conversion of design's layout and placement into set of masks e.g.diffusion, contact, and metallization masks etc., Phase 3: Mask Transfer -This involves transferring the mask set onto a wafer substrate such as Si or GaAs etc., Phase 4: Packaged Chip -This incorporates inscribing, dicing, bonding and encapsulating chip in a plastic or ceramic package, depending on customer's requirement.At UMass Lowell, the author founded the Microelectronics/VLSI program in 1984, at the time, when only design tool available was DLAP (intense programming tool in PASCAL for layout and placement).In 1985 UC Berkeley provided free MAGIC, a layout and placement tool through Massachusetts Microelectronics Center (M 2 C).In order to enhance the design capabilities UMass Lowell received a donation of $28m from Cadence and 50% discount from SUN on sparc stations, with a promise to pay $5k to Cadence for license agreement, which is cardinal stone of Phase I since 1998.Phase II has not been achieved yet at UMass Lowell due to budgetary constraints.Phase 3 however, was consummated in its entirety through Distributed Semiconductor Instructional Processing Laboratory (DSIPL), a unique facility established at UMass Lowell in 1986 with a grant of $1m by M 2 C along with the clean room facility because of the former president Bill Hogan's funds.The test mask for this endeavor was provided by National Institute of Science and Technology (NIST), wherein students in the course VLSI Fabrication transfer the mask to fabricate the MOSFET on a Si wafer, and carry out in-situ testing as well as exhaustive testing in all stages of processing including Oxidation, Lithography, Diffusion, Metallization etc. Phase 4: This phase was not also accomplished because of budgetary and space problems at our place so far.