Novel VLSI Architecture for Discrete Wavelet Packet Transform Using Arbitrary Tree Structures

The paper presents a novel pipelined VLSI architec- ture based on an arbitrary wavelet tree for the calculation of the discrete wavelet packet transform (DWPT) of any signal. There are phases of calculating the coefficients for different levels. For each level, there is a bypassed wavelet filter and a circuit for rearranging intermediate coefficients. The recommended lifting- based wavelet filter computes the high and low pass coefficients in series. It either calculates the coefficients or passes the samples such that there is an allowance of the arbitrary tree topology. A subband necessary for the higher-level computation is generated by rearranging the intermediate coefficients. The coefficients are computed progressively, and the circuit complexity diminishes with the reduction of intermediate coefficients other than memory components. A 50 percent decrease in memory components is needed with the pipelined design presented above. Also, data from hardware implementation clearly suggest that the space and power needs have gone reduced by 20% and 33%, respectively. Index Terms—Arbitrary tree structure, bitreordering, discrete wavelet packet transform (DWPT), signal flowgraph (SFG).