Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit

• Efficient ternary multiplexer : The paper introduces an efficient ternary multiplexer (TMUX) as a key component in ternary adders and multipliers, aiming to reduce power consumption and transistor counts while maintaining low noise sensitivity. • CNTFET technology : All ternary circuits in the design use CNTFET (Carbon nanotube field-effect Transistor) technology, leveraging its variable threshold properties to achieve different logic levels. • Performance improvements of TMUX : The proposed TMUX shows significant improvements, with up to 98 % reduction in average power consumption and up to 99 % improvement in power-delay product (PDP) compared to existing designs. • Transistor count and power efficiency : The proposed ternary half-adder (THA) reduces transistor count by up to 64 %, while improving power efficiency by 9.5 % to 99 %. It also achieves up to 93 % reduction in delay and 99 % improvement in PDP. • Ternary multiplier (TMUL) enhancements : The proposed TMUL reduces the transistor count by up to 60 % and improves average power, delay, and PDP by up to 91 %, 13 %, and 92 %, respectively, compared to existing designs. The NMs of proposed TMUL has improved by 60 % in comparison to existing designs. This article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon nanotube field-effect transistor technology to achieve all levels due to the variable threshold property. The proposed ternary circuits have been evaluated and compared to state-of-the-art designs in the literature using the HSPICE simulator. The average power consumption of the proposed ternary multiplexer has improved up to 95 %. The average power of the proposed ternary half adder is improved by 99 % and the power-delay product of it is reduced up to 99 %. The proposed ternary multiplier and ternary half adder have reduced the transistor count by up to 60 % and 36 % respectively, in comparison to existing designs. The delay of the proposed ternary multiplier and ternary half adder has been reduced by up to 13 % and 93 %, respectively.