A Stable Dual Second Order Generalized Integrator Phase-Locked Loop System for Grid Synchronization by Means of Anti-Windup Limiter

This paper presents an improved stable dual second-order generalized integrator phase-locked loop (DSOGI-PLL) system for grid synchronization, incorporating an anti-windup limiter. The DSOGI-PLL system can become unstable or malfunction during transient interruptions in power generation, significant frequency steps due to severe grid faults, exposure to a wide range of frequency fluctuations, or low frequencies. The proposed structure, referred to as DSOGI-AW-PLL, integrates an anti-windup (AW) limiter within the phase-locked loop (PLL). This improvement stabilizes the DSOGI-PLL system, preventing it from tripping and losing synchronization under frequency fluctuations. This paper discusses the issues with the DSOGI-PLL system, particularly its tendency to become stuck under distorted grid conditions, explores the causes, and proposes a solution. Additionally, the DSOGI-AW-PLL system is analyzed using both clamping and back-calculation anti-windup methods. Various simulation results are presented, with performance and stability evaluated and compared under different frequency fluctuations and distorted grid operations.