Efficient Parallel Simulation of Networked Synchronous Discrete-Event Systems
We present Sitar, an open-source, general-purpose modeling framework consisting of a custom modeling language and a simulation kernel, designed for efficient parallel simulation of networked Synchronous Discrete-event Systems (SDES) in applications such as communication networks and computer systems design. A unique feature of Sitar is its two-phase, cycle-based simulation algorithm that allows an efficient, race-free parallel execution on shared-memory systems. This is achieved by imposing a mild restriction on the set of SDES that can be described within the framework. The modeling language is designed for describing complex, networked systems with a static interconnection structure. We demonstrate Sitar's modeling capability, performance and scalability through a detailed performance evaluation and a comparison against SystemC and SimPy. Our results show that Sitar's single-threaded performance is better than that of SimPy and comparable to that of SystemC, whereas a multi-threaded execution shows near-linear scaling for several benchmark configurations.
Authors
- Madhav P. Desai
- Neha Karanjkar (ORCID: https://orcid.org/0000-0003-3111-1435)
- Akhil Kushe
- Anish Natekar
Institutions
- Indian Institute of Technology Bombay (IN)
- Indian Institute of Technology Goa (IN)
Publication Details
- Published
- 2024-12-15
- DOI
- https://doi.org/10.1109/wsc63780.2024.10838747
- Primary Topic
- Simulation Techniques and Applications
- Type
- article
- Field-Weighted Citation Impact
- 0.00