Design and Implementation of a NTT Accelerator Based on RISC-V for PQC Kyber

RISC-V, as a new generation open-source Reduced Instruction Set Computing (RISC) architecture, has the advantages of low power consumption, small footprint, and high performance. Especially, RISC-V processors realized based on FPGA can be applied in different fields such as embedded systems, Artificial Intelligence (AI) chips, security devices and high-performance computing. It is foreseeable that a breakthrough in quantum computers will jeopardize all communications. Therefore, processors must integrate secure quantum computer anti-encryption techniques. Currently, the security and reliability aspects of processor implementations are still greatly underexplored. To address this gap, we propose three contributions. First, we augment the open-source IP Hummingbird E203 with a hardware module for implementing the Number-Theoretic Transform (NTT) operations of the Post-Quantum Cryptography (kyber). Second, we employ the hardware/software co-design techniques to accelerate NTT operations. Third, analyze the results of implementation. Prototyping was performed on FPGA to evaluate our designed processor NTT extension instructions. The cycle count for NTT operations is reduced by 84.55% and the instruction count is reduced by 81.25%. Enhanced computational efficiency applicable to information security systems under potential quantum computing threats is shown. The scalability of Post-Quantum Cryptography (kyber) based on riscv is realized.