An Analog Neural Computing Unit Circuit Design with $2\times 2$ MAC Based on CMOS for Storage-Computing Integration

This paper presents a Neural Computing Unit (NCU) design with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\times 2$</tex> analog multiplier accumulation circuit which can achieve convolution and pooling operations for DNN algorithm. It has the function of integrating data storage and computation, which greatly improves energy efficiency of the chip for artificial intelligence processors. Using 180-nm CMOS process technology, an analog neural computing unit circuit has been designed in Cadence, including a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\times 2$</tex> multiplier accumulation circuit, digital to analog convertors, and voltage-to-time converters. Simulation results verify the convolution operation function. Meanwhile, storage-computing integration is also realized by this circuit. The performances of the designed NCU have also been evaluated and analyzed. The error of computing is within 5% on different corners and temperatures.