MATLAB-Based Performance Verification of 2.4-GHz All-Digital Sub-Sampling PLL with −125 dBc/Hz In-Band Noise
This paper presents a MATLAB and Simulink model for a 2.4 GHz All-Digital Sub-Sampling Phase-Locked Loop (ADSSPLL) which could meet the strict demands of IoT equipment. The proposed ADSSPLL uses Sub-Sampling Phase Detectors (SSPD) to replace the high-resolution Time-to-Digital Converter (TDC) and avoid using the frequency divider which could greatly improve the in-band noise and reduce the loop complexity. MATLAB and Simulink tools are used to verify the circuit performance of ADSSPLL. With the reference frequency at 50 MHz, the In-Band Noise is measured to −125 dBc/Hz@1 MHz, and it achieves a Root-Mean-Square (RMS) output jitter of 347 fs.
Authors
- Xin Yu (ORCID: https://orcid.org/0000-0002-9072-6862)
- Xu Liu (ORCID: https://orcid.org/0000-0001-7366-0649)
- Zhijie Chen (ORCID: https://orcid.org/0000-0002-6546-7352)
- Peiyuan Wan (ORCID: https://orcid.org/0000-0003-4875-6432)
- Liangjian Lyu (ORCID: https://orcid.org/0000-0002-6157-0109)
Institutions
- Beijing University of Technology (CN)
Publication Details
- Published
- 2024-11-01
- DOI
- https://doi.org/10.1109/asid63618.2024.10839691
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- Natural Science Foundation of Beijing Municipality
- Beijing Municipal Science and Technology Commission