FFT Processor for 3D Imaging

3D imaging technology has developed rapidly and been widely applied in recent years, and Fast Fourier Transform (FFT) is a key component of 3D imaging technology. With the increasing demand for 3D-FFT scale and speed, data storage planning is the guarantee for imaging speed in large point 3D-FFT. In 3D-FFT, computations are required along three axes, and when the scale is large, data must be stored off-chip. As a result, when computing along the third axis, we will face the problem of crossing address access to stored data, significantly reducing 3D-FFT efficiency. The traditional method requires a total of six memory access operations, reading and writing along the X, Y, and Z axes individually, which ultimately fails to meet the bandwidth requirements. This paper proposes a 3D data storage scheme and address mapping strategy specifically for 3D-FFT data, along with a method to improve DDR data efficiency. These innovations reduce the number of memory accesses and improve the efficiency of memory access during cross-row addressing. To meet high throughput demands, a 16-parallel 256-point FFT structure and a 16-parallel transposition method are designed, improving the overall system performance from 60.902 ms with traditional methods to 33 ms, thereby meeting the 30 FPS performance requirement.