FPGA for High-Frequency Trading: Reducing Latency in Financial Systems
High-Frequency Trading (HFT) has revolutionized modern financial markets by executing large volumes of trades at extreme speeds, where even microsecond-level improvements can lead to significant gains. Traditional software-based systems running on CPUs and GPUs face limitations in achieving the low latencies demanded by HFT. In this research work, we propose a Field-Programmable Gate Array (FPGA)-based system to reduce latency and enhance performance in high-frequency trading environments. By leveraging the parallelism and hardware acceleration capabilities of FPGAs, Our system achieved an average latency of 480 nanoseconds, significantly outperforming CPU and GPU-based implementations. Additionally, the FPGA-based system demonstrated high throughput, processing up to 150,000 orders per second while consuming considerably less power than its counterparts. These results highlight the potential of FPGA technology to transform HFTby providing low-latency, high-throughput solutions, ultimately enabling faster and more efficient trading systems.
Authors
- R. Naresh
- A. Purohit (ORCID: https://orcid.org/0000-0003-0881-612X)
- D. Bakshi Gupta
Institutions
- SRM Institute of Science and Technology (IN)
Publication Details
- Published
- 2024-12-04
- DOI
- https://doi.org/10.1109/icacrs62842.2024.10841781
- Citations
- 1
- Primary Topic
- Numerical Methods and Algorithms
- Type
- article
- Field-Weighted Citation Impact
- 0.36